Biography
Publications

Education Background

 Ph.D. University of Wisconsin, Madison

Research Field

Optimizing Compilers, Dynamic Binary Translation and Optimization, Virtualization and Virtual Machines, High Performance Computer Architectures

Biography

Wei Chung Hsu received his PhD degree in computer science from the University of Wisconsin, Madison, in 1987. Prior to joining the SDS, CUHKSZ, he was working at Intel, USA. From 2021 to 2022, he was a consultant at the Andes Technology. From 2013 to 2021, he was a professor at the department of Computer Science and Information Engineering, at the National Taiwan University. From 2009 to 2013, he was a professor and director at the National Chiao-Tung University, Taiwan, China. From 1999 to 2009, he was a professor at the Computer Science and Engineering Department, at University of Minnesota, Twin Cities. From 1997 to 1999, he was a runtime optimization architect in the California Language Lab, at Hewlett Packard Company. From 1993 to 1997, he was a technical lead in the compiler team which developed and released an optimizing compiler for the HP PA-8000 systems. Prior to joining HP, he was a senior architect at Cray Research, in Chippewa Falls, Wisconsin.

Selected Conference Papers

  1. Yi You, Pangfeng Liu, Ding-Yong Hong, Jan-Jan Wu and Wei-Chung Hsu “Accelerating Convolutional Neural Networks via Inter-operator Scheduling”, IEEE ICPADS, 2022, (Best Paper runner up).
  2. Yu-Ping Liu, Ding-Yong Hong, Jan-Jan Wu, Sheng-Yu Fu, and Wei-Chung Hsu, “Exploiting Asymmetric SIMD Register Configurations in ARM-tox86 Dynamic Binary Translation”,26th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT), Portland, Oregon, USA, 2017
  3. Ding-Yong Hong, Sheng-Yu Fu, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu, “Exploiting Longer SIMD Lanes in Dynamic Binary Translation”, IEEE ICPADS, 2016. (Best Paper Award).
  4. Yu-Ju Huang, Hsuan-Heng Wu, Yeh-Ching Chung, Wei Chung Hsu, “Building A KVM- based Hypervisor for A Heterogeneous System Architecture Compliant System”, ACM Virtual Execution Environment, VEE’2016, Atlanta, USA, 2016, (Outstanding Paper Award).
  5. James R. Goodman and Wei-Chung Hsu: ”Author retrospective for code scheduling and register allocation in large basic blocks”. the International Conference on Supercomputing, (ICS) 25th Anniversary 2014
  6. Ding-Yong Hong, Jan-Jan Wu, Pen-Chung Yew, Wei-Chung Hsu, Chun-Chen Hsu, Pangfeng Liu, Chien-Min Wang, and Yeh-Ching Chung,” HQEMU: A Multi-Threaded and Retargetable Dynamic Binary Translator on Multicores”, Proceedings of the Tenth Annual IEEE/ACM International Symposium on Code Generation and Optimization, (CGO-2012), Apr. 2012
  7. Jiun-Hung Ding, Po-Chun Chang, Wei-Chung Hsu, Yeh-Ching Chung, “PQEMU: A Parallel System Emulator Based on QEMU”,IEEE International Conference on Parallel and Distributed Systems, ICPADS 2011, Dec., 2011 (Best Paper Award)
  8. Yangchun Luo, Venkatesan Packirisamy, Nikhil Mungre, Ankit Tarkas, Antonia Zhai, and Wei Chung Hsu, “Dynamic Performance Tuning for Speculative Threads”, Proceedings of the International Symposium on Computer Architecture, (ISCA'09), June, 2009.
  9. Jiwei Lu, Abhinav Das, Wei-Chung Hsu, Khoa Ngyuan, Santosh Abraham, "Dynamic Helper Threaded Prefetching on the SUN Ultra SPARC CMP Processor", in Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture, (MICRO-38) , 2005
  10. Jiwei Lu, Howard Chen, Rao Fu, Wei Hsu, Pen-Chung Yew, D. Chen "The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System" in Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, (MICRO-36), San Diego, California, Dec. 3-5, 2003
  11. Jin Lin,Tong Chen,Wei Hsu,Pen-Chung Yew,Roy Ju "A Compiler Framework for Speculative Analysis and Optimizations" In Proceedings of the SIGPLAN'03 Conference on Programming Language Design and Implementation (PLDI-2003), June, 2003
  12. Vatsa Santhenam, Eddie Gornish, and Wei Hsu, "Data Prefetch on the HP-PA8000", Proceedings of the International Symposium on Computer Architecture, (ISCA'97), June, 1997.
  13. Dave Dunn and Wei Hsu, "Instruction Scheduling for the HP-PA8000", Proceedings of the 29th Annual International Symposium on MicroArchitecture, (MICRO-29), Dec., 1996.
  14. Wei Hsu and Jim Smith, "Performance of Cached DRAM in Vector Supercomputers", Proceedings of the International Symposium on Computer Architecture (ISCA'93), 1993
  15. Sriram Vayapeyam and Wei Hsu, "On the Instruction-Level Characteristics of Inherently Scalar Code in Highly-Vectorized Scientific Applications", Proceedings of the 25th Annual International Symposium on MicroArchitecture, (MICRO-25), 1992
  16. Jim Smith and Wei Hsu, "Prefetching in Supercomputer Instruction Caches", Supercomputing, (SC'92), Nov., 1992.
  17. Sriram Vajapeyam, Wei Hsu and Guri Sohi, "An Empirical Study of the Cray Y-MP processor using the Perfect Club Benchmarks", Proceedings of the International Symposium on Computer Architecture, (ISCA'91), 1991.
  18. J. Goodman and Wei Chung Hsu, "Code Scheduling and Register Allocation in Large Basic Blocks" the International Conference on Supercomputing, (ICS'88), 1988.
  19. A. Pleszkun, J. Goodman, Wei Chung Hsu, ate. al., "WISQ: A Restartable Architecture Using Queues" Proceedings of the International Symposium on Computer Architectures, (ISCA'87), 1987.
  20. J. Goodman and Wei Chung Hsu, "On the Use of Registers vs. Cache to Minimize Memory Traffic", Proceedings of the International Symposium on Computer Architectures, (ISCA'86), 1986